The present invention generally relates to semiconductor materials and to a method of reducing the propagation of threading dislocations from plastic deformation in mismatched epitaxial layers into active areas of optoelectronic devices and, more particularly, to a method for reducing the propagation of such dislocations for solar energy conversion and other photovoltaic devices.
The interest in photovoltaic (PV) cells in both terrestrial and non-terrestrial applications continues as concerns over pollution and limited resources increases. Irrespective of the application, and as with any energy generation system, efforts have been ongoing to increase the output and/or increase the efficiency of PV cells. To increase the electrical power output of such cells, multiple subcells comprising layers having different energy band gaps have been stacked so that each subcell or layer can absorb a different part of the wide energy distribution in the sunlight. This situation is advantageous, since each photon absorbed in a subcell corresponds to one unit of charge that is collected at the subcell operating voltage, which is approximately linearly dependent on the band gap of the semiconductor material of the subcell. An ideally efficient solar cell would have a large number of subcells, each absorbing only photons of energy negligibly greater than its band gap.
Many optoelectronic devices are formed by thin film epitaxial growth of III–V compound semiconductors upon a mechanical substrate. This substrate—typically of GaAs, InP, Ge or other bulk material—acts as an atomic template for the formation of the epitaxial layers. The atomic spacing or lattice constant in the epitaxial layers is typically fixed by that of the substrate.
Devices are formed only at or near the lattice constant of an available substrate material. FIG. 1 shows the band gap of binary materials connected by lines of ternary alloys (e.g., InGaAs is a line between GaAs and InAs), as well as showing the lattice constants for most common substrate materials. A basic problem is that devices are optimal for applications in regions of band gap where there is no available substrate. For example, the theoretically most efficient solar cells are composed of alloys with band gaps that have lattice constants between GaAs and InP substrates. A similar dilemma continues to most optoelectronic devices—such as lasers, LEDs, HBTs, and others—where the most suitable band gaps are not the ones easily available near a lattice constant of an available substrate.
Another restriction this imposes is in the cost of the available substrates for a given device. For example, InP is available, but is very costly and may make certain optoelectronic designs too expensive to be commercially practical. There are two main approaches to overcoming this restriction. One approach is to grow layers that are lattice-mismatched to the substrate, but are thin enough that they are fully-strained, i.e., unrelaxed. Such layers are known as pseudomorphic layers. In such layers, the band gap and other properties may be adjusted by virtue of the ability to alter the lattice constant and semiconductor composition, as well as by the strain state of the pseudomorphic layers, thereby allowing the device performance to be improved. But the thickness of these layers that can be grown before plastic deformation occurs is typically limited. A second approach is to grow an inactive buffer that is completely or nearly completely relaxed, and then growing the rest of the device on top of this layer as if it were a substrate with a new lattice constant. These layers which transition from the lattice constant of the growth substrate to a new lattice constant upon which strain-free layers can be grown are known as metamorphic layers. In general, devices grown with such intentionally relaxed layers are known as metamorphic devices.
Pseudomorphic layers are routinely used in optoelectronics to enhance performance in all device types. The device designs are limited to layers where no relaxation or limited relaxation has occurred and thus limited to certain amounts of strain and thickness. That strain and thickness relationship is typically dictated by the Matthews-Blakeslee relationship (described in Matthews, J. W. and Blakeslee, A. E.: “Defects in epitaxial multilayers, I. Misfit dislocations”, J. Crystal Growth, 1974, 27, pp. 118–125 and incorporated herein by reference) which describes the equilibrium thickness, which may be exceeded depending on kinetics. In the Matthews-Blakeslee model, dislocation formation occurs when an epilayer exceeds a critical strain energy density. Once formed, dislocations move as an atomic level crack through the remaining epitaxial layers in a form known as a threading dislocation. When plastic deformation occurs, it may occur to a limited degree (partial relaxation) or completely (total relaxation). Both are generally termed as “metamorphic” layers.
In epitaxy, when a layer relaxes, it does so by forming edge dislocations at the boundary between the strained layer and the substrate. The conventional view of the process is called the dislocation glide model. As the thickness of the growing mismatched layer increases, the surface strain increases. When the strain energy reaches a critical value, the layer begins to relax by forming a loop or ½ loop made up of two threading dislocation segments and an edge dislocation segment at the free surface of the strained layer. In vapor-phase epitaxy, this free surface is the growth front or solid-vapor interface. The loop then propagates the edge dislocation to the strain layer/unstrained layer interface where the edge segment stops. The threading segments extend from that interface to the free surface. Continued growth of the mismatched layer builds additional strain. Simultaneously, the additional strain may be relieved by the extension of the existing edge segments or by the formation of more dislocation loops. Once formed, the threading dislocations then propagate throughout the rest of the growth layers, whether the layers exceed the critical strain energy or not. In other words, the defects become a permanent feature of the upper epitaxial layers. Understanding how to control this relaxation and the limitation it presents is essential in growing mismatched epitaxial layers.
The density of edge-dislocations required for 100% relaxation at the strain layer/unstrained layer interface is determined by the difference in lattice constant of the two layers. The number or density of loops is a kinetic or rate problem. The final threading dislocation density generated is determined by the balance between the extension of existing dislocation loops and the nucleation of new loops. One may extend the thickness and/or strain of a pseudomorphic mismatched layer beyond that described by the Matthews-Blakeslee limit by slowing down this rate of loop formation.
The presence of threading dislocations in the active regions of a device may act as a loss mechanism, degrading the performance of the device. Unbonded atoms at threading dislocations act as recombination centers reducing the minority-carrier lifetime in the device active regions. This is especially true for devices where minority carrier lifetime is important such as photovoltaic (PV) cells, laser diodes (LDs), light emitting diodes (LEDs), and heterojunction bipolar transistors (HBTs). The need for low recombination rates in such devices usually necessitates that these devices be grown at lattice-matched conditions. However, if the layer is thin enough, no dislocations are formed. This thickness requirement restricts the usefulness of intentionally engineering the strain within a given device to near atomic layer dimensions for large strains. Alternatively, for thicker epitaxial structures required for entire devices, the mismatch in lattice constant must be very small. Typically, the inplane strain, ε∥, is limited by ε∥<0.1%, where ε∥ is of a mismatched epitaxial layer defined by ε=|alayer−asubstate|/alayer, and where alayer and asubstate are unstrained lattice constants of the layer and substrate, respectively.
One may attack the problem of strained, mismatched active device layers by controlling the growth conditions and composition to keep the designed layers below the strain and thickness parameters. As stated above, this limits the available alloys and thicknesses for device designs and may be highly disadvantageous for device performance. The other extreme in this problem is to intentionally form 100% relaxed layers, but confine the relaxation to inactive regions of the device. This method is the metamorphic buffer layer approach. In this method, layers are grown in a manner that “forces” relaxation to occur, such as growing at large mismatches and thicknesses. The remaining layers are grown lattice-matched to this new lattice constant. The drawback to this method is that forcing the relaxation to occur typically leads to large densities of threading dislocations in the remaining layers, which then propagate into the upper, active regions of the device, lowering performance of any device grown on top of it. Many methods of prior art exist in attempting to control the density of dislocations in the active regions of metamorphic devices.
general method that has been found to minimize the threading dislocation density in a metamorphic device is to grow a buffer layer with a graded lattice constant. The strain at the surface during growth may be kept less than one percent with respect to the already relaxed portion of the grade. This low strain typically produces relaxation by the dislocation glide mechanism rather than the three-dimensional islanding often seen at high strains. Minimization of threading dislocation density is a complicated optimization process as evidenced by Fitzgerald et al in U.S. patent application Ser. No. US2001/0040244. The rates of dislocation glide, dislocation pinning and dislocation nucleation are all dependent on the chosen process parameters. The rates generally increase with temperature, but it is the competition between them which determines the result. Thus, process design to obtain low dislocation density is not straight forward. Other design parameters such as heavy (>˜1018 cm−3) n-type doping may affect the structure by hardening the material, hindering both dislocation glide and possibly nucleation.
Multijunction photovoltaic cells are a specific category of optoelectronic devices that would benefit strongly from the freedom to choose semiconductor band gaps for its constituent layers, independent of the band gaps of semiconductor compositions that can readily be grown on available growth substrates such as Ge, GaAs, InP, Si, and GaSb. Lattice-matched 2-junction GaInP/GaAs solar cells [Olson, U.S. Pat. No. 4,667,059; Olson and Kurtz, U.S. Pat. No. 5,223,043] and 3-junction GaInP/GaInAs/Ge solar cells [King et al., “High-Efficiency Space and Terrestrial Multijunction Solar Cells Through Bandgap Control in Cell Structures,” Proc. 29th IEEE Photovoltaic Specialists Conf., May 20–24, 2002] have been described in the literature. Lattice-mismatched 2-junction GaInP/GaInAs/GaAs cells [Dimroth et al., “25.5% Efficient Ga0.35In0.65P/Ga0.83In0.17As Tandem Solar Cells Grown on GaAs Substrates,” IEEE Electron Device Lett., Vol. 21, p. 209 (2000)] and lattice-mismatched 3-junction GaInP/GaInAs/Ge solar cells [King et al., “Metamorphic GaInP/GaInAs/Ge Solar Cells,” Proc. 28th IEEE Photovoltaic Specialists Conf. (IEEE, New York, 2000), p. 982] have also been described. Additionally, lattice-mismatched multijunction cells with III–V subcells combined with an active silicon substrate, such as 3-junction GaInP/GaInPAs/Si cells; transparent, graded buffer layers such as GaPAs or GaInP to transition from the substrate lattice constant to the device lattice constant in such cells; and multiple graded buffer layers placed between upper and lower subcells, as well as between substrate and lower subcells, to provide maximum flexibility in subcell lattice constant and band gap, are also described in the literature [King et al., U.S. Pat. No. 6,340,788]. All of the above lattice-mismatched multifunction photovoltaic cell designs have a need for, and would benefit from, a structure or method which inhibits propagation of dislocations from the metamorphic (lattice-transitioning) layers into the active regions of the device, since these dislocations act to reduce minority-carrier lifetime, and thereby reduce photovoltaic cell performance.
In the case of 2- or 3-junction (2J or 3J) GaInP/GaInAs/Ge solar cells, the entire epitaxial stack is typically grown at or near lattice-matched conditions with respect to the Ge substrate. In terms of the epitaxial materials, this means limiting the indium content to approximately 1 atomic percent in the GaInAs layers and keeping the indium content of the GaInP layers to near 49.5 atomic percent, +/−1 percent. Since the epitaxial layers are much thicker than the critical thickness for threading dislocation formation, strong deviation from these alloy concentrations leads to losses of open circuit voltage (Voc), voltage at maximum power (Vmp), fill factor, and hence, of efficiency. However, the band gaps of GaInAs and GaInP grown lattice-matched to a Ge (or GaAs) substrate are not exactly tuned to the solar spectrum to produce the most efficient device possible. If GaInAs and GaInP can be grown at a different lattice constant than that of the Ge substrate, thereby modifying the GaInAs and GaInP subcell bandgaps, the photovoltaic conversion of the space and terrestrial solar spectra is theoretically much more efficient. The maximum theoretical AMO efficiency for GaInP/GaInAs/Ge triple-junction solar cells in which the top and middle subcells are lattice-matched to each other is approximately 38%, attained at a GaInAs middle cell indium content of 12%, i.e., a Ga0.40In0.60P/Ga0.88In0.12As/Ge triple-junction solar cell. These intentionally lattice-mismatched devices are categorized as metamorphic photovoltaics. These mismatched structures are considerably less mismatched than the structures of other metamorphic InGaAs devices. The demands for structural perfection in minority-carrier devices such as solar cells are higher than those for most other devices.
Solar cell device performance is a good indicator of relative defect density in the epitaxial layers. The open circuit voltage (Voc) is determined by the minority-carrier lifetime through the relationship:
      V    oc    =            nkT      q        ⁢          ln      ⁡              (                                            J              sc                                      J              sat                                +          1                )            where k is the Boltzmann constant, T is the temperature, q is the electronic charge, Jsc is the short circuit current density, n is the diode ideality factor, and Jsat is the saturation current density of the diode which depends directly on the minority-carrier lifetime. Since the minority-carrier lifetime depends strongly on the relative defect density, so will the open-circuit voltage. Similar relations follow for other device parameters such as fill factor (FF), and short circuit current (Jsc). Small changes in open-circuit voltage result from an exponential change in defect density. Qualitatively, an increase in dislocation density decreases all of the basic solar cell parameters in illuminated current-voltage (I–V) measurements: Voc, FF, and Jsc.
Previous research into middle-cell-active-only Ga0.88In0 12As epitaxial layers grown on a relaxed buffer layer graded from the Ge lattice constant to that of the middle cell has shown that the best performing devices lose 200 mV of voltage as compared to the lattice-matched cells. Only 100 mV of loss is expected due to the reduction of band gap due to the increased indium. Additionally, the cells lose fill factor as well. These effects demonstrate the losses in performance due to recombination in threading dislocations propagating into the middle cell from the relaxed GaInAs buffer layer. Overall, these losses combine to limit the performance of full 3J metamorphic devices to approximately 27 to 28 percent efficient, much less than the theoretical predictions for no-loss devices.
There has been considerable interest in the growth of highly mismatched epilayers in both the SiGe and III–V material systems. Typical attempts to grow highly strained epilayers result in a transition to three-dimensional growth “islanding” after a few monolayers soon after exceeding the Matthews-Blakeslee thickness.
A method of avoiding this “islanding” in the system of Ge on a Si substrate has been discovered by Copel et al., U.S. Pat. No. 5,628,834. They show the use of dopants in Ge and Si such as arsenic or antimony, which act as surfactants, to maintain two-dimensional growth of highly strained Ge/Si structures at temperatures between 400 and 700° C., with greater layer thicknesses than possible by other methods. However, Copel et al. use surfactants in the system of Ge on a Si substrate where the Ge layer exceeds 3 to 6 monolayers. Accordingly, the process by Copel et al. is used for extremely lattice-mismatched layers where large strains cause a transition to islanding growth. But there is no suggested application to significantly different material systems or to layers with small strains to maintain pseudomorphic layers and control plastic extended-line defect nucleation.
In III–V semiconductor growth, dopants have been used as surfactants in work performed by Massies et al. “Surfactant mediated epitaxial growth of InxGa1−xAs on GaAs (001),” Appl. Phys. Lett., Vol. 61 (1992) p. 99, where tellurium , an n-type dopant in III–V semiconductors, was added to InGaAs to extend the critical thickness of the epitaxial layers. Tellurium has been seen as the analog in III–V systems to the antimony used in the group-IV SiGe system, since they are both n-type dopants in these respective semiconductor systems, which interact strongly with the surface. Both also strongly segregate at the growing surface of growing films. This analogy was reinforced by the failure of tin, an isoelectronic element in group-IV systems, which segregates on the growing surface of Si to suppress islanding in the SiGe system.
In a variation of this method, U.S. Pat. No. 6,139,629 to Kisielowski et al. disclose the use of bismuth and similar group-V atoms to reduce the growth temperature for high-quality group-III/nitride (III-N) semiconductors. As disclosed, bismuth acts to reduce the onset of islanding growth in III-N epitaxy at reduced growth temperatures. Again, however, there is no suggested application to small strains to maintain pseudomorphic layers and control plastic extended-line defect nucleation. A similar idea of using an isoelectronic surfactant to extend the two-dimensional growth regime of III–V semiconductors has been used in extending the strain in InGaAs and InGaAsN quantum wells for laser diodes by Shimizu et al. in “1.2 μm Range GaInAs SQW Lasers Using Sb as Surfactant,” Electron Dev. Lett., Vol. 36, (2000) p. 1379, and references therein. However, the authors never offer that an isoelectronic surfactant changes the dislocation kinetics. In other words, they do not teach the application of this work to metamorphic, relaxed epitaxial layers. They only deal directly in applying the idea to create highly strained, unrelaxed layers. Their principal observation is that the Sb suppresses the transition to three-dimensional growth.
Another attempt to minimize threading dislocations is shown by Liu et al., “High-quality Ge films on Si substrates using Sb surfactant-mediated graded SiGe buffers,” Appl. Phys. Lett., Vol. 79, No. 21, 19 Nov. 2001 (3431). The graded SiGe films were grown at about 500° C., and Sb was used as an n-type dopant surfactant. Conditions were expected to result in a highly n-doped SiGe buffer. Liu et al., however, did not suggest applying the process beyond their IV—IV material system to other material systems, such as a III–V material system. Their explanation of the effect is that the n-type surfactant aids the motion of the misfit dislocations. They did not suggest that any surfactant would have an impact upon the dislocation nucleation kinetics.
An excellent overview of the current state of the art of processes to maintain a low threading location density and relaxed growth template in III–V semiconductors by fabrication of relaxed InGaAs buffers on GaAs substrates is disclosed in U.S. patent application Ser. No. US2001/0040244 to Fitzgerald. The disclosed process utilizes metalorganic chemical vapor deposition (MOCVD) to grow the relaxed graded layers at a temperature ranging upwards from about 600° C. However, Fitzgerald does not suggest the use of surfactants (e.g., Te) for n-type doping even though the disclosure follows after Copel et. al. and Liu et. al. which teach the use of surfactant doping. A similar discussion of the growth of InGaP/GaP alloys is given in is given in Kim and Fitzgerald US2001/0047751.
As can be seen, there is a need for a method of reducing the propagation of threading dislocations from plastic deformation in mismatched epitaxial layers into active areas of optoelectronic devices, particularly III–V devices. Such a method preferably can be applied to improve the performance of devices utilizing metamorphic layers. Further, such a method preferably can be applied to reduce substrate costs by improving the performance of lattice-matched layers upon poorer quality or less expensive substrates.